(
		clk,
		reset,
		led

);
		input clk;
		input reset;
		output	[3:0]	led;
		
//**********内部ノード**************//
		parameter		sec_1= 32'h01F78A40;
		reg	[3:0]	led_pattern;
		reg	[31:0]	sec_cnt;
		
//***************内部回路**************//

always @(posedge clk)
begin
		if(reset == 1'b1) begin
			led_pattern <=4'b1110;
		end else begin
			if( sec_cnt == sec_1 ) begin
				sec_cnt <= 32'h00000000;
				led_pattern[0] <= led_pattern[3];
				led_pattern[1] <= led_pattern[0];
				led_pattern[2] <= led_pattern[1];		
				led_pattern[3] <= led_pattern[2];
			end else begin
				sec_cnt <= sec_cnt + 1;
			end
		end
end

		assign	led[3:0]	= led_pattern[3:0];
				
endmodule