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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:23:48 02/28/2009 
-- Design Name: 
-- Module Name:    led_shift - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

--*******************入出力ピン定義************************--
entity led_shift is
	Port	(	clk	:	in	std_logic;
				reset	:	in	std_logic;
				led	:	out	std_logic_vector(3 downto 0)
			);
end led_shift;
	
--**********************アーキテクチャ***********************--

architecture Behavioral of led_shift is
	
	signal	led_pattern : std_logic_vector(3 downto 0);
	signal	sec_cnt		: std_logic_vector(31 downto 0);
	signal	sec_1			: std_logic_vector(31 downto 0):=X"01F78A40";
begin
	process(clk,reset)
		begin
		if(clk'event and clk='1')then
			if(reset='1') then
				led_pattern <= "1110";
			else
				if(sec_cnt = sec_1) then
					sec_cnt <= X"00000000";
					led_pattern(0) <= led_pattern(3);
					led_pattern(1) <= led_pattern(0);
					led_pattern(2) <= led_pattern(1);
					led_pattern(3) <= led_pattern(2);
				else
					sec_cnt <= sec_cnt + 1;
				end if;
			end if;
	end if;
	end process;
	
	led <= led_pattern;
	
end Behavioral;